1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including a plurality of lanes of processing circuitry which perform processing operations in parallel with each other, for example, single instruction multiple data (SIMD) processing systems.
2. Description of the Prior Art
It is known to provide data processing systems which incorporate a plurality of processing lanes for performing in parallel data processing operations upon respective operands. An example of such a system is a SIMD system, but other examples include other forms of vector processor and special purpose processors, such as those which may be used to extract pixel values from texture maps within graphics processing units. An advantageous feature of such processing systems including a plurality of lanes of processing circuitry is that high levels of data throughput may be achieved, e.g. individual colour component values for pixels may be processed in parallel rather than having to be processed separately in series. It is often, but not always, the case that the processing operation performed is the same for each of the lanes of processing circuitry. A disadvantage of systems employing a plurality of lanes of processing circuitry is that the circuit area consumed by the processing circuits can be large resulting in an increase in cost, complexity, power consumption and the like.
An issue that arises in the above systems is that operand dependent special case conditions (not opcode dependent) may arise which require special case processing operations to be performed within the lanes of processing circuitry. Examples of such operand dependent special case conditions in the context of processing floating point numbers are if any of the operands being processed are denormal operands, not-a-number (NaN) operands, operands requiring formal conversion (especially narrowing conversions) and the like. In order to deal with the special case processing operations which can arise in any of the plurality of lanes of processing circuitry, one approach is to provide special case handling circuits within each of the plurality of lanes of processing circuitry. Each of these special case handling circuits can then deal with any special case conditions arising for the operands being processed within its lane of processing circuitry. A problem with this approach is that the special case handling circuits add circuit area, cost and complexity to the overall system. These special case handling circuits are present within each of the plurality of lanes of processing circuitry thereby increasing the effect they have on the overall system circuit area. While these special case handling circuits may be necessary to perform required special case processing operations, such special case processing operations are relatively rare in normal processing. This has the consequence of the special case handling circuits consuming a relatively high circuit area to provide functionality that is rarely used.
Another approach is to support the special case processing operations in software when they arise. This is disadvantageously slow.